In mobile devices such as mobile phones and digital cameras, SiP (System in Package) in which a plurality of chips are stacked and mounted in a semiconductor package is widely used. When the chips are disposed in the manner that they are stacked, the mounting area can be reduced compared with the case in which they are horizontally disposed. Moreover, a large number of chips can be mounted in the same mounting area. However, when the chips are mutually connected by bonding wires, the wiring space for once suspending the bonding wires is needed in a chip peripheral region, and thus the mounting area becomes larger than the chip size. Moreover, there are problems that resistance and inductance are increased as the bonding wires are long and that this is not suitable for high-speed operations.
In order to solve these problems, development of silicon through-electrode techniques for directly connecting chips by forming electrodes which penetrate through the inside of the chips is underway. In this structure in which the chips are mutually and directly connected, the wiring space is not needed in the chip peripheral part, and the space of the mounting area thereof can be reduced. Furthermore, since the inter-chip wiring is the shortest, the wiring resistance and inductance can be suppressed low, and high-speed operations can be carried out.
For example, Japanese Patent Application Laid-Open Publication No. 2000-260934 reports the technique in which, after forming through-holes in chips, through-electrodes are formed by embedding solder or a low-melting-point metal by electrolytic or electroless plating method, and the chips are mutually connected by melting the embedded metal by heating.
Moreover, for example, Japanese Patent Application Laid-Open Publication No. 2007-53149 reports the technique in which a bump formed on an upper chip is pressed against a hollow through-electrode formed in a lower chip to cause the bump and the through-electrode to undergo plastic deformation, so that the bump and the through-electrode are physically caulked so as to mutually connect the chips.
Conceivable methods of forming the above-described bump include a stud bump method and a plating bump method. For example, Japanese Patent Application Laid-Open Publication No. 2007-73919 discloses a method of forming a bump having a sharp end by the plating bump method. Such bump has a high deformability and is suitable for the inter-chip connection technique described in the above-mentioned Patent Document 2.
In the technique of the above-mentioned Patent Document 2 studied by the inventors of the present invention, the through-electrode is formed from a back surface of a semiconductor wafer after semiconductor elements, multi-layer wirings, and bonding pads are formed on a main surface of the semiconductor wafer. When the through-electrode is formed at the end in this manner, the influence on the device caused by particles and contamination generated upon formation of the through-electrode can be reduced, and the designing and manufacturing processes of the device and multi-layer wiring are not required to be changed. Moreover, there is also a big advantage that the through-electrode can be treated as a part of the packaging technique, for example, the through-electrode can be manufactured even in an existing product chip for which inter-chip wiring by wire bonding is expected.
On the other hand, in order to electrically connect the device, which is formed on the semiconductor wafer main surface, and the through-electrode to each other, the through-electrode and a bonding pad have to be electrically connected to each other. The bonding pad is disposed on the surface of an interlayer insulating film. In order to form the through-electrode from the back surface, a hole which penetrates through the silicon substrate part and the interlayer insulating film and stops at the bonding pad surface is formed. The through-electrode can be formed in this manner.
However, according to further studies carried out by the present inventors about the method of forming the through-electrode described above, it has been found out that the method has below problems. When a hole is to be formed from the back surface of the silicon substrate in order to form the through-electrode, as the processability of the interlayer insulating film per se, which is positioned in a lower layer, is low and the part disposed on the bottom surface of a deep hole formed in the silicon substrate is to be processed, etching species does not readily enter. Furthermore, the etching has to be stopped at the point it reaches the thin bonding pad.
As a technical trend of the future, it is conceivable that the degree of integration of the devices mounted on semiconductor devices will be increased and that the number of the through-electrodes formed per one chip will be increased. As a result, the through-electrode will have a small diameter and a high aspect ratio. Given such background, it has been found out that it would be difficult to form the hole portion for the through-electrode only by the back-surface processing. The difficulty of processing the through-electrode and the need for higher processing techniques are the cause that lowers the productivity of above-mentioned high-performance semiconductor devices.